The present invention relates to a Pulse Code Modulation (PCM) translator for translating a PCM input word into a PCM output word, one of said words being in accordance with a compressed code and the other with a linear code.
An object of the present invention is to provide a translator of this type which is adapted to selectively perform the translation according to the A-law or to the mu-law and nevertheless is of a relatively simple structure.
According to the invention this object is achieved due to the fact that it is adapted to convert the binary bits of the input word into those of the output word in accordance with either the A-law or the mu-law as given by the selectable binary value of a control bit which determines the digital values of several parameters of the translator.
By the use of the selectable control bit value the translator is able to selectively perform a translation according to the A-law or to the mu-law and because this bit controls several parameters of the translator the latter may be given a simple structure which is substantially the same for both laws.
Another characteristic feature of the present translator is that it it able to translate a compressed PCM input word including a 3-bit segment code and a 4-bit step code into a linear PCM output word by determining the function EQU J=(L+a.multidot.2.sup.4 +b.multidot.2.sup.-1).multidot.2.sup.K' +c
wherein
J is said output word; PA1 L is said step code; PA1 a, b and c are variables; PA1 K' is related to said segment code and is dependent, together with said variables a, b and c, on said control bit (A) indicating that said input word is coded according to the A-law or mu-law. PA1 J is said input word; PA1 K is said segment code; PA1 L is said step code; PA1 c and d are variables PA1 K' is related to said segment code and is dependent together with c and d on said control bit (A) indicated that said output word is coded according to the A- or mu-law.
From this function it follows that the operations to be executed for the A-law and the mu-law are very similar and only differ in details due to which it is possible to use for both laws a same structure for the translator, as already mentioned.
Still another characteristic feature of the last mentioned translator is that it includes:
decoder means for decoding said 3-bit segment code into a 1-out-of-8 code S7, S6, . . . , S'1, S'.0.;
logic means coupled to said decoder means and controlled by said control bit and providing the variables: EQU a=S'.0.+A EQU b=S'.0.(S'1+A) EQU S.0.=S'.0..multidot.A EQU S1=S'.0..multidot.A+S'1
the code word S7, . . . , S1, S.0. constituting an altered segment code having a decimal value K';
means for modifying said step code L by said variables a and b so as to obtain an altered step code EQU L+a.multidot.2.sup.4 +b.multidot.2.sup.-1
multiplier means coupled to said modifier means for multiplying said altered step code with 2.sup.K' so as to obtain the product (L+a.multidot.2.sup.4 +b.multidot.2.sup.-1).multidot.2.sup.K'
and adder means coupled with said multiplier means and controlled by said control bit to add said variable c to said product so as to obtain said output word J.
The translator is thus able to perform a translation either according to the A-law or to the mu-law under the control of the selectable control bit and by the use of relatively simple logic means.
Yet another characteristic feature of the present translator is that it is adapted to translate a linear PCM input word into a compressed PCM output word including a 3-bit segment code and a 4-bit step code by determining the functions EQU K=Log.sub.2 [(J+c).multidot.2.sup.-4 ] EQU L=(J+c).multidot.2.sup.-K' -d
wherein
From these functions it again follows that the operation to be executed for the A-law and the mu-law are very similar and only differ in details due to which it is possible to use for both laws a same structure for the translator.
Still another characteristic of the last mentioned PCM transcoder is that is includes:
adder means controlled by said control bit to add said variable c to said input J to obtain an altered input word J+c and store it in a shift register;
decoder means coupled with said shift register for decoding the 8 most significant bits of said altered input word J+c into a 1-out-of-8 code S7, S6, . . . , S'1, S'.0. but by taking only the activated bit of highest power of said altered input word into account;
encoder means coupled to said decoder means for coding said 1-out-of-8 code into said 3-bit segment code K;
logic means which are coupled to said decoder means and controlled by said control bit and which provide the variables: EQU S.0.=S'.0..multidot.A EQU S1=S'.0..multidot.A+S'1
the code word S7, . . . , S1, S.0. having the decimal value K';
multiplier and adding means for multiplying said altered input word J+c by 2.sup.-K' and adding said variable -d to this product so as to obtain said step code L.
The invention also relates to a shift register cell with a data input coupled to a data output through the cascade connection of an input storage circuit and an output storage circuit. This shift register cell is characterized in that it also has an auxiliary data input, said auxiliary data input and the output of said first storage circuit being coupled to the input of said second storage circuit via respective first and second gating means having a common control input and such that they are always in an opposite state of conductivity.
The invention further also relates to a multiplier device for multiplying a binary word stored in a first shift register with 2.sup.x, with x=.0., . . . K, by shifting said word through x stages of said shift register.
This multiplier device is characterized in that said second shift register includes K stages, that the output of said first shift register is coupled with the K stages of said second shift register via K respective first gating means which are controlled by respective bits of a binary 1-out-of K code which has said decimal value x, and that to each of said stages is associated a second gating means, the second gating means being controlled by said respective bits all in such a way that when a first gating means establishes a connection between the output of the first shift register and a stage of the second shift register, the latter stage is isolated from the other stages of this shift register by the second gating means associated therewith.